Musings on CMOS basics

Where did CMOS come from and how did old CMOS chips get made, with large gate lengths, I mean, they now at 30nm in production with Intel



The reason is a p-n junction is made of a metal for the contact and conduction of electricity, and oxide for insulation to establish a potential difference and a semi-conductor that is doped p-type and another n-type, hence complimentary to each other’s type of doping, to establish drift, diffusion and a depletion region.
They are wide spread in portable devices such as camera’s due to the use of photodiodes which are sensitive to light and can generate current, thus acting as sensitive detectors/ switches of photons, depending on how they are arranges and connected. They are relatively inexpensive to manufacture on a large scale due to the maturity of such devices in the computing industry, where established lithography and fabrication techniques have been perfected over the years and feature sizes have been following Moore’s law.
With slight modifications these transistors can be addressed very easily with an electrical grid system, which is sufficient for transporting and processing the information carried across the wires and establishing an addressing system.

(a) A switch is a simple MOS p-n junction, when there is a bias voltage the switch is on as there is a conduction path between the terminals.
An inverter is two switches connected in series.
A latch is an arrangement of switches that can be set into two different states and provides an electrical output, can be set to either state electrically and is also stable.
Two switches will create an inverter, for CMOS memory this is not practical as it will store the opposite state desired, so a 1 would be a 0 and vice versa and also the output is indeterminate. The solution is 4 switches, so that there are two inverters, one feeding the other, this is what is used to create a memory latch, So sending a 1 or 0 will result in a 1 or 0 being stored on the output and it is determinate, so loss of power will keep the output the same.2
No drain will occur when a switch is open, as the conducting path through the gate terminal has no applied bias applied.

(b) Most of the process steps in the fabrication of CSMOS require photolithography to define areas that are etched or deposited. The photolithography uses a photoresist polymer which is then exposed to UV light and the weaker parts of the resists are washed off, producing a positive or negative depending on the resist used. Resolution of features are limited by these photolithography.
To create CMOS we will need an adjacent p-well and n-well, kitted out with their respective components:

· Gate oxide

· Gate

· Source

· Drain

· P+ Substrate and p layer

· Electrical contacts

One of the most important factors is the gate length and the doping requirements used for these gates.

Some of the challenges involved are:

v Isolating switches from each other

o The p-Type and N-Type switches need to be isolated from each other, this is achieved by Shallow Trench Isolation. The isolation trenches are etched around 400nm deep into the silicon using LPCVD for the sacrificial layer.

o Then a plasma etch is used to form the trenches. This trench is the barrier between switches. There must be no sharp points so the STI etch agent used is HBrO2.

o The trenches must be filled with an insulator, which uses CVD process and the chemical TEOS. The capacitance between each switch has an impact on the speed and power of the chip, so the dielectric constant of the insulator must be as low as possible.

v Defining wells and the role of photolithography

o Wells are the doped silicon which will form the junction with the source and drain contacts. Alternating p/n type wells are masked off by photolithography. Ion bombardment implants donor or acceptor atoms in the silicon surface. The doping stage defines the polarity of the final channel and the sign of the gate voltage used to activate the switch. So the doping concentrations must be correctly applied.

o Width on old chips is around 200nm, new ones will be much smaller now.

v Formation of the Gate Oxide (Insulator)

o The integrity of the gate oxide to act as a insulator is crucial, as electrical breakdown must not occur here. The trick is to control the thickness of the gate oxide to be as thin as possible and use a high quality oxide with high-k dielectrics, due to the capacitance affecting the performance of the device. This oxide is deposited using conventional lithography techniques and uniformity is crucial to a quality gate oxide. The gate length will be in the region of 250nm, which will sit on top of this oxide. The thickness is around 1.2 +- 0.5 nm . With new techniques we looking at 30nm production quality as of 2010.

v Making electrical connections to the switches

o Metals can be deposited using sputter deposition such as PVD. Advanced PVD is needed here to ensure a high degree of directionality, where control of sidewall angle is need for criss-cross grid system, CL2/HBr plasma sis appropriate for this.

This is due to the fact that reducing the gate length will reduce the power consumption of the chip and also allows creating faster gate architectures by increasing the number of transistors in the chip, so smaller feature sizes means more processing power. We need oxides with a High-K dielectrics, hafnium oxide is a promising material since it has a dielectric constant which is 5 times more than silica, this means we can have 5 times the capacitance at the price of the same thickness!


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